The trend for semiconductor devices is smaller integrated circuit (IC) devices (also referred to as chips), packaged in smaller packages (which protect the chip while providing off chip signaling connectivity). With related chip devices (e.g. an image sensor and its processor), one way to accomplish size reduction is to form both devices as part of the same IC chip (i.e. integrate them into a single integrated circuit device). However, that raises a whole host of complex manufacturing issues that can adversely affect operation, cost and yield. Another technique for combining related chip devices is 3D IC packaging, which saves space by stacking separate chips inside a single package.
3D packaging can result in increased density and smaller form factor, better electrical performance (because of shorter interconnect length which allows for increased device speed and lower power consumption), better heterogeneous integration (i.e. integrate different functional layers such as an image sensor and its processor), and lower cost.
However, 3D integration for microelectronics packaging faces challenges as well, such as high cost of 3D processing infrastructure and sustainable supply chain. Existing 3D IC packaging techniques to form through-silicon via's (TSV's), including Via-First, Via-Last and Via-middle processes, utilize semiconductor lithographic processes which are inherently complex and costly. As a result, few companies in the world can afford the billions of dollars in CMOS R&D per year to keep pace. Moreover, interconnects between IC packages can fail due to the stresses incurred during manufacturing and mounting, as well as thermal or vibrational stresses incurred during operation. A complementary, cost-effective TSV solution is needed to enable use of a separate hut closely coupled image processor enabling the pixel array area on the image sensor to be maximized, and enable direct memory access, by stacking and vertically interconnecting multiple chips.